Programmable analog floating gate circuits have been used since the early 1980's in applications that only require moderate absolute voltage accuracy over time, e.g., an absolute voltage accuracy of 100-200 mV over time. Such devices are conventionally used to provide long-term non-volatile storage of charge on a floating gate. A floating gate is an island of conductive material that is electrically isolated from a substrate but capacitively coupled to the substrate or to other conductive layers. Typically, a floating gate forms the gate of an MOS transistor that is used to read the level of charge on the floating gate without causing any leakage of charge therefrom.
Various means are known in the art for introducing charge onto a floating gate and for removing the charge from the floating gate. Once the floating gate has been programmed at a particular charge level, it remains at that level essentially permanently, because the floating gate is surrounded by an insulating material which acts as a barrier to discharging of the floating gate. Charge is typically coupled to the floating gate using hot electron injection or electron tunneling. Charge is typically removed from the floating gate by exposure to radiation (UV light, x-rays), avalanched injection, or Fowler-Nordheim electron tunneling. The use of electrons emitted from a cold conductor was first described in an article entitled Electron Emission in Intense Electric Fields by R. H. Fowler and Dr. L. Nordheim, Royal Soc. Proc., A, Vol. 119 (1928). Use of this phenomenon in electron tunneling through an oxide layer is described in an article entitled Fowler-Nordheim Tunneling into Thermally Grown SiO2 by M. Lenzlinger and E. H. Snow, Journal of Applied Physics, Vol. 40, No. 1 (January, 1969), both of which are incorporated herein by reference. Such analog floating gate circuits have been used, for instance, in digital nonvolatile memory devices and in analog nonvolatile circuits including voltage reference, Vcc sense, and power-on reset circuits.
FIG. 1A is a schematic diagram that illustrates one embodiment of an analog nonvolatile floating gate circuit implemented using two polysilicon layers formed on a substrate and two electron tunneling regions. FIG. 1A illustrates a cross-sectional view of an exemplary prior art programmable voltage reference circuit 70 formed on a substrate 71. Reference circuit 70 comprises a Program electrode formed from a first polysilicon layer (poly1), an Erase electrode formed from a second polysilicon layer (poly2), and an electrically isolated floating gate comprised of a poly1 layer and a poly2 layer connected together at a corner contact 76. Typically, polysilicon layers 1 and 2 are separated from each other by a thick oxide dielectric, with the floating gate fg being completely surrounded by dielectric. The floating gate fg is also the gate of an NMOS transistor TØ shown at 73, with a drain D and a source S that are heavily doped n+ regions in substrate 70, which is P type. The portion of dielectric between the poly1 Program electrode and the floating gate fg, as shown at 74, is a program tunnel region (or “tunnel device”) TP, and the portion of dielectric between the polyl floating gate fg and the poly2 erase electrode, shown at 75, is an erase tunnel region TE. Both tunnel regions have a given capacitance. Since these tunnel regions 74,75 are typically formed in thick oxide dielectric, they are generally referred to as “thick oxide tunneling devices” or “enhanced emission tunneling devices.” Such thick oxide tunneling devices enable the floating gate to retain accurate analog voltages in the +/−4 volt range for many years. This relatively high analog voltage retention is made possible by the fact that the electric field in most of the thick dielectric in tunnel regions 74,75 remains very low, even when several volts are applied across the tunnel device. This low field and thick oxide provides a high barrier to charge loss until the field is high enough to cause Fowler-Nordheim tunneling to occur. Finally, reference circuit 70 includes asteering capacitor CC that is the capacitance between floating gate fg and a different n+ region formed in the substrate that is connected to a Cap electrode.
FIG. 1B is a schematic diagram that illustrates a second embodiment of a floating gate circuit 70 that is implemented using three polysilicon layers. The three polysilicon floating gate circuit 70′ is similar to the two polysilicon embodiment except that, for example Erase electrode is formed from a third polysilicon layer (poly 3). In addition, the floating gate fg is formed entirely from a poly2 layer. Thus, in this embodiment there is no need for a corner contact to be formed between the poly1 layer portion and the poly2 layer portion of floating gate fg, which is required for the two polysilicon layer cell shown in FIG. 1A.
Referring to FIG. 2, shown at 25 is an equivalent circuit diagram for the voltage reference circuit 70 of FIG. 1A and 70′ of FIG. 1B. For simplicity, each circuit element of FIG. 2 is identically labeled with its corresponding element in FIGS. 1A and 1B.
Setting reference circuit 70 to a specific voltage level is accomplished using two separate operations. Referring again to FIG. 1A, the floating gate fg is first programmed or “reset” to an off condition. The floating gate fg is then erased or “set” to a specific voltage level. Floating gate fg is reset by programming it to a net negative voltage, which turns off transistor TØ. This programming is done by holding the Program electrode low and ramping the n+ bottom plate of the relatively large steering capacitor CC to 15 to 20V via the Cap electrode. Steering capacitor CC couples the floating gate fg high, which causes electrons to tunnel through the thick oxide at 74 from the poly1 Program electrode to the floating gate fg. This results in a net negative charge on floating gate fg. When the bottom plate of steering capacitor CC is returned to ground, this couples floating gate fg negative, i.e., below ground, which turns off the NMOS transistor TØ.
To set reference circuit 70 to a specific voltage level, the n+ bottom plate of steering capacitor CC, the Cap electrode, is held at ground while the Erase electrode is ramped to a high voltage, i.e., 12 to 20V. Tunneling of electrons from floating gate fg to the poly2 Erase electrode through the thick oxide at 75 begins when the voltage across tunnel device TE reaches a certain voltage, which is typically approximately 11V. This tunneling of electrons from the fg through tunnel device TE increases the voltage of floating gate fg. The voltage on floating gate fg then “follows” the voltage ramp coupled to the poly2 Erase electrode, but at a voltage level offset by about 11V below the voltage on the Erase electrode. When the voltage on floating gate fg reaches the desired set level, the voltage ramp on poly2 Erase electrode is stopped and then pulled back down to ground. This leaves the voltage on floating gate fg set at approximately the desired voltage level.
As indicated above, reference circuit 70 meets the requirements for voltage reference applications where approximately 200 mV accuracy is sufficient. The accuracy of circuit 70 is limited for two reasons. First, the potential on floating gate fg shifts down about 100 mV to 200 mV after it is set due to the capacitance of erase tunnel device TE which couples floating gate fg down when the poly2 Erase electrode is pulled down from a high voltage to ØV. The amount of this change depends on the ratio of the capacitance of erase tunnel device TE to the rest of the capacitance of floating gate fg (mostly due to steering capacitor CC), as well as the magnitude of the change in voltage on the poly2 Erase electrode. This voltage “offset” is well defined and predictable, but always occurs in such prior art voltage reference circuits because the capacitance of erase tunnel device TE cannot be zero. Second, the accuracy of circuit 70 is also limited because the potential of floating gate fg changes another 100 mV to 200 mV over time after it is set due to various factors, including detrapping of the tunnel devices and dielectric relaxation of all the floating gate fg capacitors.
Applications that require increased absolute voltage accuracy generally use a bandgap voltage reference. A bandgap voltage reference typically provides approximately 25 mV absolute accuracy over time and temperature, but can be configured to provide increased accuracy by laser trimming or E2 digital trimming at test. While a bandgap voltage reference provides greater accuracy and increased stability over the prior art voltage reference circuits discussed above, a bandgap voltage reference only provides a fixed voltage of about 1.2V. Therefore, additional circuitry, such as an amplifier with fixed gain, is needed to provide other reference voltage levels. Moreover, prior art bandgap voltage references typically draw a relatively significant current, i.e., greater than 10 μA.
One of the key performance parameters for precision voltage references and comparators is the temperature coefficient, Tc, which indicates how much the voltage reference output (Vref) changes over a given temperature range. Tc for a given part may be positive, negative, or may change direction over various temperature ranges. A commonly accepted method of specifying Tc for voltage references is the “Box Method”. The Box Method uses the maximum voltage and the minimum voltage of the reference voltage generated within a given temperature range, regardless of the specific temperature at which the minimum or maximum occurs in the range. This method is independent of the polarity or change in polarity of Tc within the specified temperature range. Usually expressed in ppm/C, i.e., ppm per degree C., Tc=106×(Vmax−Vmin)/(Vref×(Tmax−Tmin)), where Vmax is the maximum voltage, Vmin is the minimum voltage, Vref is the voltage reference output, Tmax is the maximum temperature in the specified temperature range, Tmin is the minimum temperature in the range, and 1 ppm/C is 10−6.
Voltage references and comparators based on bandgap and buried zener devices typically have temperature coefficients in the 10 to 20 ppm per degree C. range using this industry standard box method of measuring Tc. For a typical bandgap voltage of 1.25V and the industrial temperature range of −40 C to +85 C, a Tc=10 ppm/deg C means the output reference voltage can vary as much a 10−5×1.25V×125 C=1.56 mV over the full temperature range. If this bandgap voltage is amplified by 4 to make a 5V reference, the output reference voltage can change up to 6.2 mV over the full temperature range.
Various circuit and testing techniques are used to reduce Tc. These include special circuits and devices used during test such as laser trimming, nonvolatile trimming bits, or correction table stored in nonvolatile memory. Since the temperature variation of these devices is not linear, the compensation circuits used to reduce Tc are, by necessity, also non-linear, become quite complex, and require significant test time and equipment to achieve <5 ppm per degree C. The buried zener devices provide a higher reference voltage, such as 4 to 8 volts with a lower Tc. The Tc of a 5V reference using a zener device is much lower because the amplifier gain is 1 or less, so the zener Tc is not amplified. However the Tc of zener devices is quite nonlinear, so the cost of the special nonlinear trimming circuits, test equipment and test time required to trim the Tc of a zener based reference in order to achieve <1 or 2 ppm per degree C. is quite high.
An object of the present invention is to provide a voltage reference or comparator based on charge on a floating gate where the Tc can be adjusted to a minimum level. Another object of the present invention is to provide a very low Tc over a wide range of reference or comparator voltages. Another object of the present invention is to show how the Tc of a floating gate reference can be adjusted using standard, low cost analog test equipment and methods.
The voltage of a floating gate equals the charge level on the floating gate divided by the total capacitance of the floating gate. The fundamental basis for floating gate memory technology as well as for floating gate analog devices is that the charge level on a floating gate has been proven to be very constant over many years. For example, nonvolatile memories using thick oxide tunneling devices have been produced for many years with data retention specified at more than a 100 years based on very high temperature charge loss studies. Other studies have indicated the charge loss on some flash cells is as low as a few electrons per year. Thus, the primary cause of change in a floating gate's voltage with temperature is due to the change in the floating gate's capacitance.
The Tc of a voltage reference or comparator circuit based on a floating gate also depends on the Tc of the circuit, including the Floating Gate MOS transistor threshold and mobility, the Tc of the floating gate voltage. To a first order of magnitude, the Tc of the floating gate transistor threshold and mobility can be compensated by using a differential stage with either two matched floating gate transistors or a second input transistor that matches the floating gate. Using well known design and layout techniques, a MOS differential stage with Tc less than 1 or 2 ppm/C can be achieved.
The total floating gate capacitance is made up of several capacitors, the MOS transistor gate to channel capacitor, source and drain overlap capacitors, the coupling or steering capacitor, tunnel device capacitors, and various parasite capacitors such as floating gate to substrate metal or other poly layers. To a first order of magnitude, the Tc of the total floating gate capacitance is the sum of the Tc of each floating gate capacitor times the amount of capacitance divided by the total capacitance:Tc=(Tc1×C1+Tc2×C2+Tc3×C3+ . . . )/Cfg total.
The Tc for each of the floating gate capacitors varies from process to process and depends on many factors such as the dielectric material and thickness, the temperature expansion coefficient of the underlying silicon, the doping level and profile of each of the capacitor plates, and the difference in DC voltage on the capacitor plates. The change in capacitance with DC voltage and with temperature is caused primarily by depletion effects in the semiconductor plates of the capacitor. Depletion or space charge effects in semiconductors create 2nd and 3rd capacitors in series with the dielectric capacitor which change with temperature and the polarity and magnitude of the field in the semiconductor.
The amount of change in capacitance of a capacitor with voltage is called the Voltage Coefficient (Vc). For many types of semiconductor capacitors, the Vc coefficient is quite nonlinear. The amount of change in capacitance with temperature, Tc, of a semiconductor capacitor varies significantly depending on the type of capacitor and also changes with the DC voltage. A typical floating gate EEPROM technology has 2 layers of polysilicon as well as an N+ diffusion coupling capacitor to the floating gate. In one EEPROM technology, the Tc of the poly-poly capacitor is about 20 ppm/deg C and the voltage coefficient is nearly 0. The Tc of one type of N+ diffusion to floating gate capacitor varies from −40 ppm/C to +0 ppm/C for DC voltages from 0 to +6 volts and the Vc is positive and varies from 100 to 10 ppm per volt in the 0 to +6 volt range. For another type of N+ diffusion to floating gate capacitor, Tc varies from −7 ppm/C to +7 ppm/C and the Vc varies from +100 to +10 ppm for DC voltages from 0 to +6 volts.
One method to achieve low Tc for a floating gate capacitor is to use capacitors with positive Tcs to compensate for capacitors with negative Tcs. For example, a poly-poly capacitor with a +20 ppm/C Tc can be used to balance out a coupling capacitor with −4 ppm/C Tc by making a coupling capacitor with 5 times more capacitance than the poly-poly capacitor. By making the poly-poly capacitor combined with the 5× coupling capacitor much larger than the rest of the floating gate capacitors, the Tc of the total floating gate capacitance can be made very low. Due to the change in Tc with applied DC voltage, the lowest Tc will be achieved for this method only at one specific DC voltage. In other words, for a given floating gate technology, a selection of types and sizes of floating gate capacitors can be made that will provide the lowest Tc at one specific DC voltage.
What is needed is a system and method for compensating for and thus minimizing Tc for a range of DC voltages so as to improve he accuracy of the output voltage (Vref) of a floating gate voltage reference.